S. Aravind Babu ¹, S. Babu Ramki ¹, S. Sivanantham ¹

Affiliations
1 ASIC Design Laboratory, School of Electronics Engineering, VIT University, Vellore – 632014, Tamil Nadu, IN

Abstract

The direct implementation of parallel particle swarm optimization algorithm on Field Programmable Gate Array (FPGA) is presented in this paper. In the proposed design, the particle unit architecture is independent of fitness unit and hence the particle unit is reusable and flexible for different fitness function. The parallel co-processor implementation of each particle accelerates the execution speed and reduces the operating power as compared to the software execution of the design on a general purpose processor. The proposed implementation reduces the number of registers by 2.76% and the number of look-up-tables by 0.62% on average.

Keywords

Co-processor, FPGA Implementation, Particle Swarm Optimization, Parallel Architecture.

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