Gaurav Verma ¹, Shambhavi Mishra ¹, Sakshi Aggarwal ¹, Surabhi Singh ¹, Sushant Shekhar ¹, Sukhbani Kaur Virdi ¹

Affiliations
1 Electronics and Communication Department of Engineering, Jaypee Institute of Information Technology, Noida – 201307, Uttar Pradesh, IN

Abstract

Adders are the integral part of any digital circuit operation. Optimization of adder’s supremacy along with its vicinity is a demanding chore. In this work an efficient BCD ADDER1 is analyzed in terms of power consumption by scaling the various parameters like voltage, frequency and load capacitance. In addition to this the focus is also given on the airflow of the device to reduce the power. Finally the power is reduced by sending different encoded data at the input. The proposed designs are hardened and implement by means of VHDL and Xilinx ISE (integrated Software Environment) 14.5 and validated using XPower targeting Virtex FPGA. Power consumption is discussed in terms of clock, signals, logic, input/ outputs and leakage. A comparative analysis has been shown at the end to validate the obtained results.

Keywords

BCD Adder, Low Power, Saif File, Scaling, VHDL, Xilinx

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