Indian Journal of Pure and Applied Physics

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A Novel Energy Efficient and Process Immune Schmitt Trigger Circuit Design Using FinFET Technology


Affiliations
1 Department of Electronics and Communication Engineering, Jamia Millia Islamia, New Delhi -110 025, India
2 Department of Electronics and Communication, National Instituteof Technology, Patna, Ashok Rajpath, Patna-800 005, India

Continuous scaling of MOS (Metal oxide semiconductor) devices gives rise to drastic increase in leakage power dissipation, which overall increases the total power dissipation. This happens due to increase in short channel effects. FinFET device has the capability to reduce short channel effects, hence reduces power dissipation as well. In this paper short-gate FinFET (fin type field effect transistor) based Schmitt trigger using LCNT (Leakage Control NMOS transistor) technique is proposed using ASAP7 PDK (A 7nm FinFET Predictive process design kit) at 7nm technology node and comparative analysis is provided with the one without LCNT technique. The simulated results shows that FinFET based Schmitt trigger using LCNT technique reduces average power dissipation and power delay product (PDP) by 36.97% and 35.6%, respectively compared to one without FinFET LCNT technique. The reliability analysis using Monte Carlo approach at ±10% process, voltage and temperature (PVT) variation under 3σ Gaussian distribution shows that LCNT FinFET Schmitt trigger provides better performance compared to FinFET Schmitt trigger at 7nm technology node.
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  • A Novel Energy Efficient and Process Immune Schmitt Trigger Circuit Design Using FinFET Technology

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Authors

UMAYIA MUSHTAQ
Department of Electronics and Communication Engineering, Jamia Millia Islamia, New Delhi -110 025, India
Md. Waseem Akram
Department of Electronics and Communication Engineering, Jamia Millia Islamia, New Delhi -110 025, India
Dinesh Prasad
Department of Electronics and Communication Engineering, Jamia Millia Islamia, New Delhi -110 025, India
Bal Chand Nagar
Department of Electronics and Communication, National Instituteof Technology, Patna, Ashok Rajpath, Patna-800 005, India

Abstract


Continuous scaling of MOS (Metal oxide semiconductor) devices gives rise to drastic increase in leakage power dissipation, which overall increases the total power dissipation. This happens due to increase in short channel effects. FinFET device has the capability to reduce short channel effects, hence reduces power dissipation as well. In this paper short-gate FinFET (fin type field effect transistor) based Schmitt trigger using LCNT (Leakage Control NMOS transistor) technique is proposed using ASAP7 PDK (A 7nm FinFET Predictive process design kit) at 7nm technology node and comparative analysis is provided with the one without LCNT technique. The simulated results shows that FinFET based Schmitt trigger using LCNT technique reduces average power dissipation and power delay product (PDP) by 36.97% and 35.6%, respectively compared to one without FinFET LCNT technique. The reliability analysis using Monte Carlo approach at ±10% process, voltage and temperature (PVT) variation under 3σ Gaussian distribution shows that LCNT FinFET Schmitt trigger provides better performance compared to FinFET Schmitt trigger at 7nm technology node.