Indian Journal of Pure and Applied Physics

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Cost-effective Programmable Logic Arrays Using Multilayer Structures of Decoders in QCA Framework


Affiliations
1 Department of Electronics and Communication Engineering, SRM Institute of Science and Technology, Ghaziabad-201 204, India
2 Department of Electrical Engineering, IIMT University, Meerut-250 001, India
3 Centre for Development of Advanced Computing (C-DAC), Mohali, 160 071, India
 

The emerging nanotechnology paradigm, Quantum Dot Cellular Automata (QCA) in particular, is gaining a wide recognition due to its high speed, nano feature size and considerably low power consumption. The QCA architecture not only provide potential alternative for Complementary Metal Oxide Semiconductor (CMOS) circuits but its multilayer topology facilitates an added benefit of cost efficacy and immunity towards random interference. Moreover, design of programmable logic devices in QCA is vital topromote the multi-utility and resiliency of the computing circuits. This paper presents the multilayer designs of 2×4 and 3×8 decoder circuits in QCA framework with 55.1% and 51.17% better cost efficiency respectively, over the earlier reported designs. The presented 3×8 decoder circuit is further utilized to implement Programmable Logic Array (PLA) to realize Boolean functions of adder and subtractor. The presented circuits are cost effective and showcase the significance of programmable devices in nano-computing.

Keywords

QCA; PLA; Decoder; Adder; Subtractor
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  • Cost-effective Programmable Logic Arrays Using Multilayer Structures of Decoders in QCA Framework

Abstract Views: 137  |  PDF Views: 88

Authors

Rupali Singh
Department of Electronics and Communication Engineering, SRM Institute of Science and Technology, Ghaziabad-201 204, India
Pankaj Singh
Department of Electrical Engineering, IIMT University, Meerut-250 001, India
Gurmohan Singh
Centre for Development of Advanced Computing (C-DAC), Mohali, 160 071, India

Abstract


The emerging nanotechnology paradigm, Quantum Dot Cellular Automata (QCA) in particular, is gaining a wide recognition due to its high speed, nano feature size and considerably low power consumption. The QCA architecture not only provide potential alternative for Complementary Metal Oxide Semiconductor (CMOS) circuits but its multilayer topology facilitates an added benefit of cost efficacy and immunity towards random interference. Moreover, design of programmable logic devices in QCA is vital topromote the multi-utility and resiliency of the computing circuits. This paper presents the multilayer designs of 2×4 and 3×8 decoder circuits in QCA framework with 55.1% and 51.17% better cost efficiency respectively, over the earlier reported designs. The presented 3×8 decoder circuit is further utilized to implement Programmable Logic Array (PLA) to realize Boolean functions of adder and subtractor. The presented circuits are cost effective and showcase the significance of programmable devices in nano-computing.

Keywords


QCA; PLA; Decoder; Adder; Subtractor

References