Equivalence Verification of the Digital Circuits with the Strategy of the Simulating Annealing

In this paper new algorithm for the verification of the equivalence of the sequential digital circuits is proposed in which it allocated a combinational block and a block from the state of the elements represented by D-triggers. In the construction of evaluation functions using the task of modeling of a circuit intact or defective. This is done by breaking the feedback lines and using an iterative modeling of combinatorial equivalent. This algorithm is based on a new strategy for the evolution of simulated annealing. This approach uses an iterative improvement of the properties of the one input sequence. The algorithm is presented as an iterative process for improving the properties of a potential solution. The exact formal verification of ownership equivalence is a difficult mathematical problem, for this reason we have reformulated the opposite: we show the non-equivalence of scheme. Fault-free simulation of the digital circuits is used for the estimating the quality of the potential solutions. The effectiveness of the proposed algorithm is shown by its approbation on the ISCAS-89 benchmarks.