A Comparative Analysis of Low Leakage Current Full Adder Cells for Embedded Processors

Leakage current optimization is one of the most important design criteria in current-day VLSI chips. In this paper different standby leakage reduction techniques like MTCMOS power gating, self-adjustable voltage level circuit, reverse body bias and transistor stack are proposed. The above techniques are applied to various designs of full adder cells using 28T, 24T, 10T, SERF adder, CLRCL adder and 4-bit adder circuits. This work analyses the leakage current of the circuits by varying the supply voltage from 0.5v to 1.0v. The delay in the sum and carry outputs after applying the reduction techniques are analyzed for the full adder cell. The output voltage levels of the adder cells are tabulated. The circuits are simulated using HSPICE in 90 nm process technology using BSIM4 MOSFET models. The effect of temperature on leakage current is also observed by varying the temperature from 25°C to 100°C. The leakage current decreases with all the proposed methods and the reduction are more with MTCMOS power gating technique.