FPGA based Implementation of Low Area and Power 16-bit Multiplier-Accumulator using Bypass Technique with SPST Adder using Verilog

High-speed (Multiplier- Accumulator) MAC is the core component of DSPs. As a large number of filtration, convolutions, and related operations are needed during the digital signal processing. To operate the computing mentioned above, High-speed MAC is an indispensable arithmetic unit of DSPs, and its performance directly influents the overall performance of DSPs. In this paper MAC unit consists of multiplier and accumulation modules. In multiplier module we use a FAB cell which bypasses zero input and for partial products addition we use SPST adder instead of full adders. So we proposing bypass technique with SPST adder for reducing the area and dynamic power. The modules are implemented in Verilog and code is dumped into the target device Xilinx Spartan3E xc3s500eft256-4. The proposed method reduces the area of 23.83% Number of Slices, 19.49 % Number of 4 input LUTs and 42.2% less power consumption as compared to carry save array MAC.