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Efficient Approach for Delay Analysis in Digital Circuits


Affiliations
1 Department of ECE, Tejaa Shakthi Institute of Technology for Women, Coimbatore, Tamilnadu-641659, India
     

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In this article, a fully digital system to analysis setup/hold time delays in digital circuits is presented. The digital circuit classified as two types: 1.combinational circuit, 2.sequentialcircuit.The proposed system benefits from easy to modify design, lowpower, smallarea, and simplecircuits. Delay element in digital system is timer. Her delay is propagation and contamination delay and etc. Delay analyzed in Xilinx ISE 10.1 software and ncsim in cadence tool, 

It is implemented in very large scale integration (VLSI).here I am using ISCAS 85/89 benchmark circuits. Analysis and compare the delay in combinational circuit and sequential circuit. The system continuously monitor and analysis any setup/hold time delay in the combinational/sequential data path.


Keywords

Combinational and Sequential Circuits, Hold Time, Setup Time, Timing Analysis, Digital VLSI Circuit.
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Abstract Views: 235

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  • Efficient Approach for Delay Analysis in Digital Circuits

Abstract Views: 235  |  PDF Views: 2

Authors

R. Chitra
Department of ECE, Tejaa Shakthi Institute of Technology for Women, Coimbatore, Tamilnadu-641659, India
A. Ramya
Department of ECE, Tejaa Shakthi Institute of Technology for Women, Coimbatore, Tamilnadu-641659, India
P. Vijayalakshmi
Department of ECE, Tejaa Shakthi Institute of Technology for Women, Coimbatore, Tamilnadu-641659, India
R. Prabakaran
Department of ECE, Tejaa Shakthi Institute of Technology for Women, Coimbatore, Tamilnadu-641659, India
N. J. R. Muniraj
Department of ECE, Tejaa Shakthi Institute of Technology for Women, Coimbatore, Tamilnadu-641659, India

Abstract


In this article, a fully digital system to analysis setup/hold time delays in digital circuits is presented. The digital circuit classified as two types: 1.combinational circuit, 2.sequentialcircuit.The proposed system benefits from easy to modify design, lowpower, smallarea, and simplecircuits. Delay element in digital system is timer. Her delay is propagation and contamination delay and etc. Delay analyzed in Xilinx ISE 10.1 software and ncsim in cadence tool, 

It is implemented in very large scale integration (VLSI).here I am using ISCAS 85/89 benchmark circuits. Analysis and compare the delay in combinational circuit and sequential circuit. The system continuously monitor and analysis any setup/hold time delay in the combinational/sequential data path.


Keywords


Combinational and Sequential Circuits, Hold Time, Setup Time, Timing Analysis, Digital VLSI Circuit.

References