FPGA Implementation of High Speed RC4 Algorithm

Rivest Code4 Algorithm is most popular Stream Cipher, which is widely used in many security protocols and standards due to its speed and flexibility. A few hardware implementations were previously recommended in the literature with the objective of enhancing the performance, area, or both. In this paper, a new hardware implementation of the RC4 algorithm using FPGA is proposed. The primary thought of this design is the utilization of a dual-port block RAM for image encryption in the FPGA in order to better utilize the available logic and memory resources. Joined with a new pipelined hardware implementation, the new outline accomplishes better performance. The design is portrayed utilizing Verilog HDL and synthesized and implemented using Xilinx 14.1 ISE suite for content encryption as well as Quartus-II 9.1 for image encryption of various FPGA devices. Synthesis results demonstrate that the proposed design accomplishes higher efficiency than previous implementations by diminishing area while keeping up a good throughput.