Digital Image Processing

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A Low Power Bit-Width Adapted DCT Architecture for Image Processing Applications


Affiliations
1 Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Coimbatore, Tamil Nadu, India
2 Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Coimbatore, Tamil Nadu, India
     

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2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. This paper presents DCT architecture based on bit-width selection algorithm. The algorithm assigns appropriate bit-width for different frequency components depending upon the sensitivity of the DCT coefficients. 1-D DCT operation is expressed as additions of vector-scalar products and basic common computations are identified and shared to reduce computational complexity in 1-D DCT operation. The implemented DCT architecture supports the bit-width reduction achieved by this algorithm & provides a considerable power saving with minimum image quality degradation. Moreover this DCT architecture has been implemented using carry save adder which provides minimum delay in comparison with other adders. Also this DCT architecture can achieve power savings ranging from 28% to 56% for 3 different trade-off levels.


Keywords

Discrete Cosine Transform (DCT), Dynamic Bit Width, Image Correlation, PSNR, Signal Correlation.
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  • A Low Power Bit-Width Adapted DCT Architecture for Image Processing Applications

Abstract Views: 450  |  PDF Views: 4

Authors

V. Premalatha
Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Coimbatore, Tamil Nadu, India
S. R. Sannasi Chakravarthy
Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Coimbatore, Tamil Nadu, India

Abstract


2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. This paper presents DCT architecture based on bit-width selection algorithm. The algorithm assigns appropriate bit-width for different frequency components depending upon the sensitivity of the DCT coefficients. 1-D DCT operation is expressed as additions of vector-scalar products and basic common computations are identified and shared to reduce computational complexity in 1-D DCT operation. The implemented DCT architecture supports the bit-width reduction achieved by this algorithm & provides a considerable power saving with minimum image quality degradation. Moreover this DCT architecture has been implemented using carry save adder which provides minimum delay in comparison with other adders. Also this DCT architecture can achieve power savings ranging from 28% to 56% for 3 different trade-off levels.


Keywords


Discrete Cosine Transform (DCT), Dynamic Bit Width, Image Correlation, PSNR, Signal Correlation.

References