Digital Image Processing

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VLSI Implementation of Sobel Edge Detection


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1 Department of Electronics and Communication Engineering, Sri Eshwar College of Engineering, Coimbatore, TamilNadu, India
     

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Edge detection is the process of identifying and finding sharp discontinuities in an image. Sobel edge detection algorithm is a gradient-based edge detection method, which finds edges using Horizontal Mask (HM) and Vertical Mask (VM). Sobel edge detection algorithm is selected due to its property of less deterioration in high level of noise. The proposed work uses a modified architecture by replacing 10-bit addition with 8-bit addition using shift operator for reducing the time and architecture complexity of Sobel edge detection algorithm. Additionally, low power adder is used for reducing the power consumption when the value of the operand remains constant. The adder is divided into two parts, i.e., the Most Significant Part (MSP) and the Least Significant Part (LSP). The MSP of the original adder is adjusted to include detection logic circuits. When the MSP is required, the input data of MSP remain unchanged. However, when the MSP is not required, the input data of the MSP become zeros to avoid glitching power consumption. The two operands of the MSP enter the detection-logic unit, except the adder, so that the detection-logic unit can decide whether to turn off the MSP or not. The bottleneck of fixed processor speed affects the image-processing algorithms in software implementation. This has been succeeded in dealing with the advancements in VLSI technology. The proposed work presents the design of edge detection using VHDL language.


Keywords

FPGA, Sobel Operator, Low Power Adder, EDGE Detection.
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  • VLSI Implementation of Sobel Edge Detection

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Authors

E. Pavithra
Department of Electronics and Communication Engineering, Sri Eshwar College of Engineering, Coimbatore, TamilNadu, India
P. Poonkodi
Department of Electronics and Communication Engineering, Sri Eshwar College of Engineering, Coimbatore, TamilNadu, India
V. Madhumitha
Department of Electronics and Communication Engineering, Sri Eshwar College of Engineering, Coimbatore, TamilNadu, India
D. Meenatchi
Department of Electronics and Communication Engineering, Sri Eshwar College of Engineering, Coimbatore, TamilNadu, India
S. Boopathy
Department of Electronics and Communication Engineering, Sri Eshwar College of Engineering, Coimbatore, TamilNadu, India

Abstract


Edge detection is the process of identifying and finding sharp discontinuities in an image. Sobel edge detection algorithm is a gradient-based edge detection method, which finds edges using Horizontal Mask (HM) and Vertical Mask (VM). Sobel edge detection algorithm is selected due to its property of less deterioration in high level of noise. The proposed work uses a modified architecture by replacing 10-bit addition with 8-bit addition using shift operator for reducing the time and architecture complexity of Sobel edge detection algorithm. Additionally, low power adder is used for reducing the power consumption when the value of the operand remains constant. The adder is divided into two parts, i.e., the Most Significant Part (MSP) and the Least Significant Part (LSP). The MSP of the original adder is adjusted to include detection logic circuits. When the MSP is required, the input data of MSP remain unchanged. However, when the MSP is not required, the input data of the MSP become zeros to avoid glitching power consumption. The two operands of the MSP enter the detection-logic unit, except the adder, so that the detection-logic unit can decide whether to turn off the MSP or not. The bottleneck of fixed processor speed affects the image-processing algorithms in software implementation. This has been succeeded in dealing with the advancements in VLSI technology. The proposed work presents the design of edge detection using VHDL language.


Keywords


FPGA, Sobel Operator, Low Power Adder, EDGE Detection.

References