High Throughput Implementation of Arithmetic Coding Using BPS Algorithm

In everyday life a multimedia environment is drastically increasing due to the technology development for the better image compression techniques which can be used in a wide range of applications. Implementation of SPIHT algorithm results in high quality image. The slow processing speed algorithm SPIHT can be overcome by BPS algorithm. BPS decomposes a wavelet-transformed image into 4×4 blocks and simultaneously encodes all the bits in a bit-plane of a 4×4 block. To achieve high speed architecture, fixed breadth first search algorithm is used to avoid variable scan algorithm. To improve he throughput of the arithmetic coder SPIHT algorithm is processed in parallel manner. The memory access pattern is employed for power saving purpose. The common bit detection (CBD) circuit is used to detect errors in arithmetic coding architecture. The architecture produces optimization performance at different levels of arithmetic coding. The architecture is implemented using FPGA and simulated using VHDL.