Digital Signal Processing

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Enhanced LUT for Modified Distributed Arithematic Architecture-FIR Filter


Affiliations
1 Department of Electronics Engineering, Pondicherry University, India
     

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This paper presents Enhanced LUT for Modified Distributed Arithmetic Architecture for efficient implementation of finite impulse response (FIR) filter. This technique consists of shift registers, Look Up Table (LUT) and accumulator. Based on this technique, multipliers in Fir filter are replaced with LUT. Multiplications are performed using shift operation. Performance analysis of various filter orders with filter coefficients (with Kaiser Window technique) are synthesized using Verilog HDL.

Keywords

Finite Impulse Response (FIR), Distributed Arithmetic, Look Up Table(LUT), Acumulator, Shift Registers, Configurable Logic Blocks (CLBs), Canonic Sign Digit (CSD).
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  • Enhanced LUT for Modified Distributed Arithematic Architecture-FIR Filter

Abstract Views: 212  |  PDF Views: 3

Authors

N. Vivek
Department of Electronics Engineering, Pondicherry University, India
K. Anusudha
Department of Electronics Engineering, Pondicherry University, India

Abstract


This paper presents Enhanced LUT for Modified Distributed Arithmetic Architecture for efficient implementation of finite impulse response (FIR) filter. This technique consists of shift registers, Look Up Table (LUT) and accumulator. Based on this technique, multipliers in Fir filter are replaced with LUT. Multiplications are performed using shift operation. Performance analysis of various filter orders with filter coefficients (with Kaiser Window technique) are synthesized using Verilog HDL.

Keywords


Finite Impulse Response (FIR), Distributed Arithmetic, Look Up Table(LUT), Acumulator, Shift Registers, Configurable Logic Blocks (CLBs), Canonic Sign Digit (CSD).