Efficient Clock Power Reduction using Merging Flip-Flop Technique in LFSR

Power has become a bottleneck for circuit implementation. In integrated circuits, power consumption is one of the top three challenges. Due to the massive increase of portable electronic device there is a need of low power flip flops in low power circuits. Clock power is the major dynamic power source. Our algorithms are very effective in reducing flip-flop clock power consumption. Several flip-flops can share a common clock buffer to avoid unnecessary power waste. Besides power reduction, the objective of minimizing the total wire length also is considered to the cost function. In this work the objective of minimizing power reduction and wire length reduction is extended for sequential circuits linear feedback shift register (LFSR). The flip-flop replacement without timing and placement capacity constraints violation becomes a quite difficult problem. To deal with the complexity competently this paper proposed several techniques. By using this method we can achieve 33% of overall power reduction. 23% of clock power reduction.