Hardware Efficient Transceiver Microcell Architecture of USB 2.0 for High Speed Data Communication Using FPGA

In this paper USB 2.0 transceiver architecture using innovative approach presented for high speed data communication. Implemented Universal Serial Bus (USB) Transceiver Macro cell is well suited for high speed data communication and also capable of handling data output relative to input as high as what USB 2.0 demands. Design is implemented on hardware of a Spartan-3FPGA. High-speed to access peripheral interfaces like USB 2.0 is coded in Veriog HDL. Result shown paper hardware efficient and test bench verification is done.