A Fast Locking ADPLL for Power Reduction through Feed Forward Compensation Technique

All digital Phase locked loops (ADPLL) plays a major role in System on Chips (SoC).Many EDA tools are used to design such complicated ADPLLs. It operates on two modes such as frequency acquisition mode and phase acquisition mode. Frequency acquisition mode is faster compared to phase acquisition, hence frequency synthesis is performed. The CMOS technology is used to design such a complex design in Micron Technology. The frequency of the ADPLL is synthesized using feed forward compensation techniques .All the parameters of ADPLL (Power consumption, area, locking time) are obtained using 0.18μm technology. The synthesis of ADPLL with Digitally Controlled Oscillator (DCO) and modified digitally programmable delay element (DPDE) are done and it is found that ADPLL with DPDE consumes less power compared to ADPLL with DCO.