An Efficient Implementation of 128 Bit Carry Save Adder

This paper present a technology independent design and simulation of a modified architecture of the carry save order it require a minimum of logic gates binary addition is carried out by series of XOR, AND and shift left operations. These operations are terminated with a computer signal indicating that the result of addition is obtained. because the number of shift operation carried out and varies from 0 to n for n bit addends the method was developed in all the possible addends of 2 to 15 bits the mathematical model was detected and used to predict the number of shifts required for binary numbers such as 32.68 or 128 bits it is used in both synchronous and asynchronous modes of operation.