Implementation of High Speed Secure Communication Between Multiple FPGA Systems Using RTOS

Reconfigurable system like FPGA platform has the potential to provide the performance benefits of ASICs and the flexibility of processors. FPGA based embedded system have become a platform for the implementation of cryptographic algorithms. In this project we are going to implement cryptographic algorithm utilizing threads run by an RTOS [Real Time Operating Systems] on FPGA systems. Since RTOS is an efficient tool to optimize the software runtime as the code complexity grows, by distributing the tasks into multiple threads. As an RTOS we have chosen Xilkernel and SEA [Scalable Encryption Algorithm] for implementing Cryptographic algorithms.

Our project mainly focus on the major issue that two threads running separately on each board can communicate with each other via RS232 communication link. The system that is used for establishing the serial communication between the multiple FPGA systems is UART (universal Asynchronous Receiver Transmitter).The proposed architecture is simulated using Modelsim and synthesized using Xilinx ISE 13.2 and it will be implemented on XC3S500e Spartan 3E FPGA board for hardware implementation and testing. The Xilinx Chip scope tool will be used to test the FPGA inside results while the logic running on FPGA .The necessary software for this design is written using the feature-rich c/c++ code editor and compilation environment provided within the SDK.