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PCI Configuration based Data Security Architecture and Co-Design Techniques


Affiliations
1 Electronics and communication Department, Dr.M.G.R. University, Chennai, Tamil Nadu, India
2 Federal Institute of Science and Technology, Ernakulam, Kerala, India
     

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The recovery of intentional/ unintentional modification of data is conventionally done by creating a backup/copy of data prior to its modification. Alternately, In this paper, the data recovery process is performed by contextually switching the semaphores to control the system resources. The designed hardware is placed in the PCI slot between the CPU and lower-level peripherals. A binary semaphore controls the data flow between the designed hardware and the CPU, whereas a mutually exclusive (context-switching) semaphore controls the data flow between the designed hardware and lower-level peripherals. The semaphore management mechanisms are moved from the application to the physical and data-link communication layers. A fully distributed management scheme is implemented, and there is no need to place the semaphore control structures on a particular node in the network. The existing version of the selected data file is copied and directed to a non-readable area of the secondary storage. This ensures retrieval of the former contents of the data file via Linked Link concept if the current modification is not authenticated.


Keywords

ASIC Chip, Context Switching, Operating System, Peripheral Component Interconnect, SRAM.
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  • PCI Configuration based Data Security Architecture and Co-Design Techniques

Abstract Views: 224  |  PDF Views: 1

Authors

Dilip Thomas
Electronics and communication Department, Dr.M.G.R. University, Chennai, Tamil Nadu, India
K. S. M. Panicker
Federal Institute of Science and Technology, Ernakulam, Kerala, India

Abstract


The recovery of intentional/ unintentional modification of data is conventionally done by creating a backup/copy of data prior to its modification. Alternately, In this paper, the data recovery process is performed by contextually switching the semaphores to control the system resources. The designed hardware is placed in the PCI slot between the CPU and lower-level peripherals. A binary semaphore controls the data flow between the designed hardware and the CPU, whereas a mutually exclusive (context-switching) semaphore controls the data flow between the designed hardware and lower-level peripherals. The semaphore management mechanisms are moved from the application to the physical and data-link communication layers. A fully distributed management scheme is implemented, and there is no need to place the semaphore control structures on a particular node in the network. The existing version of the selected data file is copied and directed to a non-readable area of the secondary storage. This ensures retrieval of the former contents of the data file via Linked Link concept if the current modification is not authenticated.


Keywords


ASIC Chip, Context Switching, Operating System, Peripheral Component Interconnect, SRAM.