Efficient Run-Time Task Allocation for Reconfigurable Multiprocessor System-On-Chip with Network-On-Chip

In this paper, we propose a SOPC (System on a Programmable Chip) design based on multicore embedded system. Under our proposed scheme, in addition to conventional processor cores, we introduce dynamically reconfigurable accelerator cores to boost the performance of the system. We have built the prototype of the system using FPGAs (Field-Programmable Gate Arrays). Simulation results demonstrate significant system efficiency of the proposed system in terms of computation and power consumption. Our approach is to develop a highly flexible and scalable network design that easily accommodates the various needs. This paper presents the design of our NoC (Network on Chip) which is a part of the platform that we are developing for a reconfigurable system.