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High Speed Reliable Serial Data Transmission Using 8B/10B


Affiliations
1 Department of Electronics & Communication Engineering, Sree Sastha Institute of Engineering & Technology, India
2 Anna University, Chennai, India
     

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An errorin a digital system is the corruption of data from its correct value to some other value. The use of error detection and correction is mandatory for all the communication systems. Power, bandwidth, delay & complexity are the major reasons for it. A small improvement in Error control can yield a large improvement in overall system. Error detection can be done in bit level, byte level and packet level. Encoders and decoders are used for physical layer coding for Gigabit Ethernet, Fibre Channel, and other. Failures can be either temporary or permanent. The effects of failures on data are predicted by error models. 8b10b having simple encoder/decoder logic is a concept of error detection and correction where long packets can be checked for error(s) in byte level accurately.

Keywords

Running Disparity, Error Correction Code, Cyclic Redundancy Check, Burst, Run Length.
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  • High Speed Reliable Serial Data Transmission Using 8B/10B

Abstract Views: 198  |  PDF Views: 3

Authors

S. Jesme Topple
Department of Electronics & Communication Engineering, Sree Sastha Institute of Engineering & Technology, India
M. Pavithra
Anna University, Chennai, India

Abstract


An errorin a digital system is the corruption of data from its correct value to some other value. The use of error detection and correction is mandatory for all the communication systems. Power, bandwidth, delay & complexity are the major reasons for it. A small improvement in Error control can yield a large improvement in overall system. Error detection can be done in bit level, byte level and packet level. Encoders and decoders are used for physical layer coding for Gigabit Ethernet, Fibre Channel, and other. Failures can be either temporary or permanent. The effects of failures on data are predicted by error models. 8b10b having simple encoder/decoder logic is a concept of error detection and correction where long packets can be checked for error(s) in byte level accurately.

Keywords


Running Disparity, Error Correction Code, Cyclic Redundancy Check, Burst, Run Length.