Performance Analysis of Domino Logic Circuits for High-Performance and Low Leakage

The Domino logic has distinct advantage over static and dynamic CMOS logic. It provides higher speed and easier testability with an inverter which can be used to overcome the inversion problem in the conventional logic design. Domino logic design improves logic flexibilities while keeping the speed and testability as intact. As noise dominates at sub-threshold level, CMOS logic design is prone at sub-threshold level. Domino logic overcomes extensive leakage issue which reduces gate level sub-threshold leakage current and improves noise immunity. In this paper, different domino logic design topologies for low leakage current at sub-threshold level are compared by increasing the noise immunity and speed. The design improves robustness and by adding "Keeper" FET, fan-in speed can be improved. Pre-charge followed by evaluation will improve the switching threshold of the Domino Logic.