Simulation of Nanoscale Gate Length with Composite Channel In0.7Ga0.3As/InAs/In0.7Ga0.3As HEMT Using Sentaurus TCAD

The aim of this work is to investigate the nanometer-gate In0.7Ga0.3As/InAs/In0.7Ga0.3 As composite-channel high-electron mobility transistors (HEMTs), which are fabricated using platinum buried gate as the Schottky contact metal, were evaluated for RF and logic application. After gate sinking at 250°C, the device exhibited a high g_m value at V_d , the current-gain cutoff frequency f_T was increased from 390 to 494 GHz, and the gate-delay time was decreased at supply voltage of 0.6 V. This is the highest f_T achieved for nm-gate-length HEMT devices. These superior performances are attributed to the reduction of distance between gate and channel and the reduction of parasitic gate capacitances during the gate-sinking process. Moreover, such superior performances were achieved through a very simple and straightforward fabrication process with optimal epistructure of the device.