A Low Power SRAM Error Compensating Cellular Automata Technique for JPEG2000

This paper presents a novel approach to reduce power in JPEG2000 implementation on multimedia devices. In order to mitigate the effect of SRAM memory failures caused by low voltage operation in JPEG2000, we investigate new scheme for designing error detecting and correcting codes around cellular automata (CA). A CA-based hardware scheme for very fast decoding (and correcting) of the codeword’s and also highly efficient, reliable and low power  compared to existing single error correction and double error detection schemes. We proposed  an algorithm-specific techniques that exploit the fact that the high frequency subband outputs of the discrete wavelet transform (DWT) have small dynamic range and so errors in the most significant bits can be identified and corrected easily. The discrete wavelet transform coefficients is used to identify and remove SRAM errors. These techniques do not require any additional memory, have low circuit overhead, and also, reduces the memory power consumption. This JPEG2000 with ECC based CA architecture is designed using Verilog HDL and simulated using ModelSim Software and Xilinx 12.1 Software.