Problems Identification & Proposed Solutions in ASIC Physical Designing

ASIC physical designing undergoes various sub level implementations like floorplanning placement routing & clock tree synthesis. Various problems being faced during physical implementation like Timing violation at certain stages of implementations, congestions occur during routing nets via various routes. Major problem of power dissipation occurring due to static and dynamic flaws. In order to make the block level or chip level design accurate and high performing above mentioned problems must be identified and solved at different stages of implementations. Various proposed solutions are been presented using which design can be made more effective and reliable. Electromigration problem identification after power planning is also important in ASIC physical designing.