Design and Simulation of Ternary Logic Gates

Ternary logic is a promising alternative to conventional binary logic. Ternary gates are therefore watched with keen interests and have attracted the attention of many researchers. Literature reports wide use of ternary universal gates to implement various combinational and sequential circuits. Efficient design and simulation of the ternary gates is therefore imperative from the perspective of a ternary processor. This paper presents the implementation and simulation of ternary gates (TNOT, TNAND, TNOR) using injected voltage method. The binary CMOS logic is exploited to achieve the ternary logic values. The proposed approach includes verification of the truth tables and simulation of the results. This research also summarizes the performance analysis of the ternary gates in terms of rise time, fall time and power dissipation. The layouts of the designed gates are also presented.