Design and Analysis of Symmetric Extended Source/Drain Schottky Tunneling Transistor

In this paper, the performance of Symmetric Extended Source/Drain Schottky Tunneling Transistor (ESD-ST-SOIFET) with different gate structures are investigated through a TCAD modeling study and compared with the performances of STSFET and conventional CMOS devices. The Symmetric Extended Source/Drain Schottky Tunneling Transistor has the source/drain regions replaced with silicide as opposed to highly doped silicon in conventional devices.The aim is to improve the on current and reduce the leakage current of the low gate length devices. It is shown that, the doped extension regions adjacent to the source/drain schottky barrier improves the drive current by shrinking the schottky barrier and also the simulation results shows that the increasing doping levels at the source/drain(S/D) extensions increases the leakage current. The optimized device shows excellent short channel immunity, compared to conventional CMOS devices. Thus the optimal S/D design for high performance is more likely to be decided by practical considerations such as process integration. The analysis also shows that, the best characteristics of the proposed device can be obtained only if using proper silicides at the S/D regions. This paper presents the simulation study of ESD-ST-SOIFET. The silicide technology can be used for the fabrication of this device. This device is considered one of the most promising candidates for future nanotechnology world.