Programmable Device Circuits and Systems

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Power Efficient Arithmetic Circuits for Application Specific Processors


Affiliations
1 MSRIT, Bangalore, India
2 Department of ECE, VSB Engineering College, Karur, India
3 AIMS, Bangalore, India
     

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This paper presents a study on RT level power optimization techniques in terms of their applicability on data-low intensive data path designs and their efficiency. The dynamic power management techniques of clock gating is investigated and their efficiency evaluated by sample designs. The static RTL power optimization methods are discussed. More specifically, the design of power efficient data path components for use in Application Specific Processors is going to be investigated.

Keywords

Clock Gating, Dynamic Power, Data Path, Simulation.
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  • Power Efficient Arithmetic Circuits for Application Specific Processors

Abstract Views: 260  |  PDF Views: 2

Authors

V. Anandi
MSRIT, Bangalore, India
R. Rangarajan
Department of ECE, VSB Engineering College, Karur, India
M. Ramesh
AIMS, Bangalore, India

Abstract


This paper presents a study on RT level power optimization techniques in terms of their applicability on data-low intensive data path designs and their efficiency. The dynamic power management techniques of clock gating is investigated and their efficiency evaluated by sample designs. The static RTL power optimization methods are discussed. More specifically, the design of power efficient data path components for use in Application Specific Processors is going to be investigated.

Keywords


Clock Gating, Dynamic Power, Data Path, Simulation.