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Power Efficient Arithmetic Circuits for Application Specific Processors
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This paper presents a study on RT level power optimization techniques in terms of their applicability on data-low intensive data path designs and their efficiency. The dynamic power management techniques of clock gating is investigated and their efficiency evaluated by sample designs. The static RTL power optimization methods are discussed. More specifically, the design of power efficient data path components for use in Application Specific Processors is going to be investigated.
Keywords
Clock Gating, Dynamic Power, Data Path, Simulation.
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