Skew Compensation Technique for Parallel Optical Interconnection for Free Distribution of Digital Signals

The clock is a periodic synchronization signal used as a time reference for data transfers in synchronous digital systems. However, the clock skew constrains the improvement of clock frequencies and affects the reliability of systems. A framing coding technique called shuffled mB1C encoding, which requires no clock rate conversion circuit and no data buffering, and a skew measurement method which is suitable for ECC adaption have been developed for the compensation. The ability to distribute signals to all parts of a circuit with precisely controlled and known delays is essential in large, high speed digital systems. This paper present a technique by which a signal driver can adjust the arrival time of the signal at the end of the wire using a pair of matched variable delay lines. The paper shows how this idea can be implemented requiring no extra wiring, and how it can be extended to distribute signals skew-free to receivers along the signal run as well as the receiving end. Paper demonstrates how this scheme can be implemented as part of the pad and scan logic of a VLSI chip. A low-latency, error correcting code-(ECC) adaptable skew-compensation technique, which is needed for high-speed and long-distance parallel optical interconnections.