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Implementation of Ray Tracing Algorithm Using Reconfigurable Platform


Affiliations
1 Department of Electronics and Telecommunication, Maharashtra Academy of Engineering, Alandi (D), Pune, India
2 Department of Electronics and Telecommunication, Maharashtra Academy of Engineering, Alandi (D), Pune, India
     

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The method in computer graphics for computing three dimensional images using virtual camera is called a rendering method. There are two popular rendering methods, commonly referred to as rasterization and ray tracing. The standard rendering method, known as rasterization, is a local illumination rendering method. In contrast ray tracing is a global illumination rendering method. In standard method of computing 3-dimentional images, advanced effects such as reflections and shadows are done using tricks and are not computed with accuracy, thus diminishing the scope for further progress in simulating real life images. This paper describe an alternative method called ray-tracing, to investigate if it can replace rasterization with capability of creating more realism. It further entails how fixed pipeline architecture can improve performance of ray-tracing algorithm. To demonstrate this idea, hardware has been designed with a fixed pipelined architecture. Ray generator entity generates rays, which passes through all the pixels in the screen. The individual ray is then tested to see whether it intersects the primitive or not and accordingly an image is formed. Design description is done using VHDL with optimized area and speed as main objectives and implementation is done on Spartan II FPGA. Demonstration is done with sphere as predefined primitive. This could further be extended in future to include reflection, shadows and simple shading operations.

Keywords

Ray Tracing, FPGA.
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  • Implementation of Ray Tracing Algorithm Using Reconfigurable Platform

Abstract Views: 189  |  PDF Views: 2

Authors

Dhanashri H. Gawali
Department of Electronics and Telecommunication, Maharashtra Academy of Engineering, Alandi (D), Pune, India
Mohit Mehta
Department of Electronics and Telecommunication, Maharashtra Academy of Engineering, Alandi (D), Pune, India
Mayank Kishore
Department of Electronics and Telecommunication, Maharashtra Academy of Engineering, Alandi (D), Pune, India
G. V. S. Tejaswi
Department of Electronics and Telecommunication, Maharashtra Academy of Engineering, Alandi (D), Pune, India

Abstract


The method in computer graphics for computing three dimensional images using virtual camera is called a rendering method. There are two popular rendering methods, commonly referred to as rasterization and ray tracing. The standard rendering method, known as rasterization, is a local illumination rendering method. In contrast ray tracing is a global illumination rendering method. In standard method of computing 3-dimentional images, advanced effects such as reflections and shadows are done using tricks and are not computed with accuracy, thus diminishing the scope for further progress in simulating real life images. This paper describe an alternative method called ray-tracing, to investigate if it can replace rasterization with capability of creating more realism. It further entails how fixed pipeline architecture can improve performance of ray-tracing algorithm. To demonstrate this idea, hardware has been designed with a fixed pipelined architecture. Ray generator entity generates rays, which passes through all the pixels in the screen. The individual ray is then tested to see whether it intersects the primitive or not and accordingly an image is formed. Design description is done using VHDL with optimized area and speed as main objectives and implementation is done on Spartan II FPGA. Demonstration is done with sphere as predefined primitive. This could further be extended in future to include reflection, shadows and simple shading operations.

Keywords


Ray Tracing, FPGA.