Implementation of 180nm CMOS Linear Feedback Shift Register (LFSR) ASIC for Data Encryption and Decryption

LFSR's are the functional building blocks of circuits like the pseudo-random noise (PN) code generator that are commonly used in Code Division Multiple Access (CDMA) systems. This application note describes two implementations of an SR4 (Shift Register) primitive for area-efficient designs LFSR using the encryption and decryption algorithms using XOR gate in 180nm for less area and low power methodologies for ASIC designs using Cadence design tools. The unusual sequence of values generated by an LFSR can be gainfully employed in the encryption and decryption of data. That makes the cryptography quite easy and useful for longer bit lengths. A stream of data bits can be encrypted and decrypted by XOR-ing them with output from an identical LFSR's which finds the certain applications like Radio and visual broad casting schemes, Internet and Wireless communications. This work mainly concentrates on the 4 bit random number that uses for encryption that is mainly works faster clock rates of  100MHz, which finds the application in wireless networks.