Modified Booth Multiplier with N/2 Partial Products Algorithm

Any VLSI circuit is composed of the very basic unit that is the multiplier. As technology is increasing day by day many new designs are being evolved. As the design becomes bigger more will be the delay in it. If the delay in the basic unit that is multiplier can be decreased then the overall delay in the new designs can be effectively alleviated. There are many multipliers designed so far in the field of VLSI using different methods for its implementation. This paper presents implementation of a Modified Booth multiplier. So far many Modified Booth multipliers are implemented. In all the methods for generating the partial products 'negi' the extra partial product bit is used due to which number of partial products generated will be N/2+1. If this 'negi' bit in the partial products can be avoided and efficient way for generating 2's complement of negative partial product is used which generates conversion signals, and then the number of partial products will decrease to N/2. For addition of partial products the design uses the 4:2 compressors to reduce the complexity in the circuit involved.