Efficient Design of SAPTL for Asynchronous Applications

This paper presents the design and implementation of a low-energy asynchronous logic topology using sense amplifier- based pass transistor logic (SAPTL). The SAPTL structure can realize very low energy computation by using low-leakage pass transistor networks at low supply voltages. The introduction of asynchronous operation in SAPTL further improves energy-delay performance without a significant increase in hardware complexity. We show two different self-timed approaches: 1) the bundled data and 2) the dual-rail handshaking protocol. The proposed self-timed SAPTL architectures provide robust and efficient asynchronous computation using a glitch-free protocol to avoid possible dynamic timing hazards. Simulation and measurement results show that the self-timed SAPTL with dual-rail protocol exhibits energy-delay characteristics better than synchronous and bundled data self-timed approaches in 180-nm, 120-nm CMOS The Pass transistor logic is a simple and compact circuit topology and in some cases, out performs static CMOS circuits. The pass transistor network itself does not have V_dd and ground connections, thus drastically reducing the number of leakage paths. In pass transistor logic (PTL), leakage is confined to the driving and level restoring circuitry associated with the PT network. These circuits are used to recover the voltage swing and delay degradation inherent in PTL circuits. A conventional PT network that implements logic functions based on multiplexer or binary decision diagram (BDD) tree structures. The main drawback of these structures is that sneak paths exists allowing leakage current to flow. PT networks can be made more complex, thus reducing the total number of drivers and level restorers in order reduce the number of leakage paths, but unfortunately, the number of sneak paths in the PT tree increases exponentially with the number of logic inputs. Note that the delay is also dependent on the number of levels and is proportional to N^2. PT also increases the effective channel length between the supply The dual-rail hand shaking protocol. The proposed self-timed SAPTL architectures provide robust and efficient asynchronous computation using a glitch-free protocol to avoid possible dynamic timing hazards. Simulation and measurement results show that the self-timed SAPTL with dual-rail protocol exhibits energy-delay characteristics better than synchronous and bundled data self-timed approaches.