FPGA Implementation of Reed-Solomon Error Correcting Code

Reed-Solomon (RS) is an error-correcting code capable of dealing with correcting multiple errors, specifically burst errors. It is form of special non binary subclass of BCH (Bose, Chaudhari and Hocqueng) codes. It can correct up to (n-k)/2 or t symbols. For a typical channel, the addition of RS coding allows the system to operate within approximately 4 dB of the Shannon capacity. The resulting benefit translates into higher data rates, lower bit error rates, greater transmission distance, and greater immunity to interference effects. Programmable-hardware devices are the best choice for Reed-Solomon codec implementation, because these devices contain an abundance of the registers that the hardware-implementation process requires. They also allow implementing a pipelined design. Secondly, parallel realization of the equations is possible and helps to meet speed constraints. Easily mapping of equations is possible on the LUT architecture of FPGAs.