Fast Parallel Multiplier-Accumulator (MAC) Architecture Based on Radix-4 Modified Booth Algorithm

In this paper we are going to propose a new merged MAC (Multiplier-Accumulator) unit using Radix 4 Modified Booth Algorithm. In this method we are going to use a hybrid type of CSA (carry save adder), this type of CSA will improve the efficiency. It will use 1’s complement number for multiplication instead of 2’s complement number. Reduced pipelining scheme can improve the Speed of the MAC. This architecture can able to perform at high speed compared to the radix 2 modified booth algorithm. The proposed architecture will synthesize with 250, 180 and 130 m, and 90 nm standard CMOS library. We will analyze the results such as the amount of hardware delay and pipelining scheme based on the theoretical and experimental estimation. The proposed MAC will show the superior properties to the standard design in many ways. Speed and performance twice as much as the previous research in the similar clock frequency.