FPGA Implementation of a Novel Data Packet Switchable HDLC Protocol

Data Transmission over any Network is prone to the possibility of transmission errors and needs to regulate the arrival rate of data to the receiver. Synchronization and interfacing technique alone are not sufficient for error free data transmission. As such, it is necessary to impose a layer of control in each communicating device to provide function such as flow control, error detection and error control. This layer of control is known as data link control. This paper presents a novel approach to design High Level Data Link control protocol (HDLC), which is most commonly used layer 2 protocol. This paper focused on the VHDL modeling of single channel HDLC layer 2 protocol and its implementation using Xillinx Sparten 3 FPGA as target device. This paper also reflects the significances of FPGA over application specific integrated circuits (ASIC) for HDLC protocol design.