An Architectural Framework for Power Performance Tuning

As device and interconnect dimensions continue to shrink and wafer sizes increase, maintaining process uniformity is increasing in importance. An understanding of variation is essential to control the process and to design manufacturable high-performance circuits. In this paper, a low-cost architectural framework for power performance testing and tuning is developed. It brings the delay and power consumption of a die within the acceptable range. Tuning “knobs” such as tunable gates are employed to deal with delay and power variations. This tuning technique improves the delay yield considerably with minimal impact on area.