Reconfigurable Carry Save Adders

Reconfigurable computing is becoming increasingly popular for many applications. In our project, we assimilate and integrate Reconfigurable adder(RA). In this project we present a novel Reconfigurable Adder for summands of different bit width (8, 16, 32 and 64 bits). The whole structure is based on carry save architecture to support multiple summands for increased performance. Our design can be implemented in ASIC as a run time reconfigurable unit. Targeting our architecture for an ASIC platform, the simulation was carried out in Cadence Incisive Unified Simulator. The synthesis done in 180 nm technology using TSMC 18d library in RTL complier. Experimental results show that RA occupies 9% area less compared to the other traditional adder.