Reconfigurable Architecture for High Performance Turbo Decoder

J. M. Mathana; J. Raja Paul Perinbam; P. Rangarajan

Reconfigurable Architecture for High Performance Turbo Decoder

J. M. Mathana ¹, J. Raja Paul Perinbam ², P. Rangarajan ³

Affiliations
1 Electronics and Communication Department, R.M.D Engineering College, Chennai–601206, India
2 Electronics and Communication Department, Professor , R.M.K Engineering College, Chennai – 601206, India
3 Information and Technology Department, Professor & Head, R.M.D Engineering College, Chennai–601206, India

This paper presents a reconfigurable architecture for high performance turbo decoder based on Max Log Maximum a Posteriori (ML-MAP) algorithm using sliding window technique. The proposed architecture is based on standardizing the branch metric values to improve the speed of operation of the decoder and also configured to support three different constraint lengths. The intended reconfigurable decoder architecture has been implemented using Verilog HDL at RTL level and synthesized to investigate its performance in terms of area usage and timing delay. The proposed technique increases the throughput rate with marginal increase in area compared to the non reconfigurable decoder.