Open Access Open Access  Restricted Access Subscription Access
Open Access Open Access Open Access  Restricted Access Restricted Access Subscription Access

Coverage Implementation for FPGAs used in Tester


     

   Subscribe/Renew Journal


This Tester Board will incorporate the functionality of Tester Instrument and will be used for testing digital baseband processors, consumer SOCs, and AC Devices. Basically tester tests the ICs by giving different inputs and verify it. It has FPGA. This Paper discusses Verification Techniques through coverage and assertion Implementation. The aim of doing is to cover and verify all the functionalities of tester FPGA Chip. (Here Tester is some client’s project name. I can’t disclose it here. It is generic name). Ultimately we are verifying Tester FPGA Chip by implementing Coverage and assertion by using new techniques.


Keywords

ASIC, SPI(Serial Peripheral Interface), DUT(Design Under Test), UVM(Universal Verification Methodology), Coverage, Assertions, Vunit,, System Verilog, FPGA, Miso(Master-in-Slave-out), Mosi(Master-out-slave-in).
User
Subscription Login to verify subscription
Notifications
Font Size

Abstract Views: 253

PDF Views: 2




  • Coverage Implementation for FPGAs used in Tester

Abstract Views: 253  |  PDF Views: 2

Authors

Abstract


This Tester Board will incorporate the functionality of Tester Instrument and will be used for testing digital baseband processors, consumer SOCs, and AC Devices. Basically tester tests the ICs by giving different inputs and verify it. It has FPGA. This Paper discusses Verification Techniques through coverage and assertion Implementation. The aim of doing is to cover and verify all the functionalities of tester FPGA Chip. (Here Tester is some client’s project name. I can’t disclose it here. It is generic name). Ultimately we are verifying Tester FPGA Chip by implementing Coverage and assertion by using new techniques.


Keywords


ASIC, SPI(Serial Peripheral Interface), DUT(Design Under Test), UVM(Universal Verification Methodology), Coverage, Assertions, Vunit,, System Verilog, FPGA, Miso(Master-in-Slave-out), Mosi(Master-out-slave-in).