Comparison of Multiplier Design with Various Full Adders

A multiplier has an important role in various arithmetic operations in the applications of digital signal processing which includes digital filtering and power analysis in the field of communication. The design of fast and low power multipliers has been a huge theoretical and practical concern for scientific researchers. In this paper the analysis of 4*4 Array and 4*4 Wallace tree multiplier and comparison is being done by using different full adders namely Conventional full adder, Transmission function full adder and Hybrid full adder. This work has been done in a schematic editor using Tanner tool v14.1 in 0.18nm CMOS technology. T-spice is used as simulator and W-editor is used to show the waveform of multiplier. The material area required to design a multiplier is reduced. Due to the reduction of material area, this causes the low power consumption, minimized area and time delay.