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Popat, Jayesh
- A Review on Various Hardware Architectures of AES Algorithm
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1 Department of Electronics and Communication Engineering, Marwadi Education Foundation, Rajkot-360003, IN
1 Department of Electronics and Communication Engineering, Marwadi Education Foundation, Rajkot-360003, IN
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Programmable Device Circuits and Systems, Vol 7, No 10 (2015), Pagination: 297-300Abstract
In recent days, the importance of security in the information technology has increased significantly. Advance Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is a cryptographic algorithm that can be used to protect electronic data. With the increasing demand for secure transaction in banking and other such system, encryption and decryption using cryptography algorithm which play a very important role. Nowadays, Most secure transactions occurring on smart phones, commercial uses and other hand-held devices, a low on chip area and a high speed algorithm to perform the same become the need for recent days. In order to achieve higher performance in today's heavily loaded communication networks, hardware implementation is a wide choice in terms of better speed and reliability. In This Review paper present the various hardware Architecture of Advance Encryption standard (AES) algorithm using Xilinx Vertex XCV1000BG560-4 Field Programmable Gate Array (FPGA).Keywords
Various Architecture of Advance Encryption Standard (Aes), Fpga.
- Speed Optimized AES Algorithm on Re-Configurable Hardware
Abstract Views :179 |
PDF Views:1
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Programmable Device Circuits and Systems, Vol 8, No 6 (2016), Pagination: 172-176Abstract
In recent days, the importance of security in IT sectors has been increased significantly. Advanced Encryption Standard (AES), is an approved cryptographic algorithm that can be used to protect electronic data. Nowadays, Most of secure transactions are occurring on smart phones, ATM transactions and other handheld devices. So that high speed algorithm to perform the same has become the need for recent days. For high speed performance in algorithm and to reduce unbreakable delay in combinational path then pipeline architecture is used. So that proposed work employs a s-box design based on pipeline Architecture synthesis and simulated on Modelsim Altera and also implemented on Altera DE-2 board. So this architecture employs a Boolean simplification of the truth table of the logic function with the aim of reducing the critical path. .The S-Box is designed using basic gates such as AND gate, NOT gate, OR gate and multiplexer. After designing of s-box based on pipeline architecture then critical path has been decreased and also increased in throughputKeywords
Advance Encryption Standard (AES), S-Box, Combinational Logic, Pipeline, FPGA- Design Procedure for Low Dropout Voltage Regulator for Portable Devices Application
Abstract Views :176 |
PDF Views:4
Authors
Affiliations
1 Department of Electronics and Communication Engineering, Marwadi Education Foundation, Rajkot, IN
1 Department of Electronics and Communication Engineering, Marwadi Education Foundation, Rajkot, IN
Source
Programmable Device Circuits and Systems, Vol 9, No 6 (2017), Pagination: 117-122Abstract
The Paper focuses on the realization of Power Efficient low voltage, low drop-out regulators these characteristics are driven by portable and battery operated products requiring compactness and low power. The approach adopted is to develop circuit techniques. As a result future and more advanced technologies will have even greater benefits and reflect the necessary sequence of event. Regulators are an essential part of any electrically powered system, which includes the growing family of applications of portable battery operated products. Regulators are required to reduce the large voltage variations of battery cells to lower and more acceptable levels. As a result, low drop-out regulators and other power supply circuits are always in high demand. In this paper design Procedure of Low Voltage Low Drop Out Voltage Regulator is Proposed and Implemented on 180nm Technology. It Discusses a 1.4 to 1.8 V 100mA CMOS Low DropOut Linear Voltage Regulator with single compensation Capacitor of 100pF. The Experimental Results show that the Maximum Output Load Current is 100mA and the Regulated Output Voltage is 1.2V. The Line Regulation is measured 4.74mV and Load Regulation measured 290uV in LTSpice Tool.
Keywords
Low Drop-Out, Low-Voltage Regulators, CMOS, Linear Regulator, Power Supply Circuits, Regulators.References
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