High Speed Floating Point Multiplier

Multiplication is a basic operation in most of the signal processing algorithms. Multipliers have large Area, long latency and consume considerable power. The purpose of a good multiplier is to provide a physically compact, good speed and should consume low power. In this paper speed of the IEEE 754 standard single precision floating point multiplier is increased by using compressors. Because compressors are special kind of adders to add more number of bits at a time. In this paper compressors are used for mantissa calculation. So that speed of the multiplier is increased as compared to the conventional multiplier. It is implemented using Verilog HDL and it is targeted to Xilinx virtex-5 FPGA.