A Systematic Approach for Design of Compressed Test Data in SOC

An efficient Software/Hardware platform to execute more number of programs the internal circuitry flow is considered. The data can be of bits-number of times the bits arriving with different time intervals. In this paper we illustrate about the compressed test data from the embedded cores in a system on a chip varies significantly during the testing process. A novel scheme has been implemented for compressed system on a chip testing based on time-multiplexing for the channels. Some/more of the channels can be introduced which can enable the sharing the data channels, on which the compressed seeds are passed to every embedded core(individual cores). The channels can be fewer/larger based on the amount of testing channels available. The uses of modular and scalable hardware for on-chip test control and test data compression have been used. We define an algorithmic model for test data compression that is applicable to system-on-chip devices comprising intellectual property-protected blocks.