A Review on Leakage Power on Fin-FET Technology

Power consumption reduction in CMOS circuits in considered as one of the most important constrain. As it not only consumes more power, reduced battery life, excessive heating, but also limits the number of transistors that can be integrated on a chip. A number of power reduction and optimization techniques for the circuits involve bulk CMOS have been analyzed in many articles. A major breakthrough in this field was achieved in 2001 in the form of FinFET. The FinFET emerges as a major solution for increasing leakage power loss in CMOS circuits designed using technologies 32nm or beyond. In this paper, I review the available power reduction optimization techniques for FinFET based designs.