Parameter Extraction of Planar Transmission Line Structure By ADI-FDTD Method

As very large scale integration (VLSI) technology shrinks to Deep Sub Micron (DSM) geometries, interconnect is becoming a limiting factor in determining circuit performance. High speed interconnect suffers from signal integrity effects like crosstalk, and propagation delay thereby degrading the entire system operation. In order to reduce the adverse signal integrity effects, if is necessary for the interconnect to have accurate physical dimensions. The interconnection and packaging related issues are main factors that determine the number of circuits that can be integrated in a chip as well as the chip performance. In this paper, it is proposed to simulate high speed interconnect structure using Alternate Direction Implicit Finite-Difference Time-Domain Method (ADI-FDTD) method.