Design and Implementation of Repair-Aware Test Flow for Multi-Memory

A complex SoC typically consists of numerous of memories in today's digital systems. This paper presents a test/repair flow based on memory grouping strategy and a revised distributed BIST structure for complex SoC devices. A gated selecting method is added to the distributed BIST structure. Also, this paper for the first time proposes a robust post repair stage based on BIRA and memory grouping in test flow. Simulation results by mathematical method show that the proposed test flow has achieved a significant increase in yield of memories.