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Integrated Task Clustering, Mapping and Scheduling for Heterogeneous Computing Systems


Affiliations
1 Macau University of Science and Technology, China
 

This paper presents a new approach for mapping and scheduling task graphs for heterogeneous hardware/software computing systems using heuristic search. Task mapping and scheduling are vital in hardware/software codesign and previous approaches that treat them separately lead to suboptimal solutions. In this paper, we propose two techniques to enhance the speedup of mapping/scheduling solutions: (1) an integrated technique combining task clustering, mapping, and scheduling, and (2) a multiple neighborhood function strategy. Our approach is demonstrated by case studies involving 40 randomly generated task graphs, as well as six applications. Experimental results show that our proposed approach outperforms a separate approach in terms of speedup by up to 18.3% for a system with a microprocessor, a floating-point digital signal processor, and an FPGA.

Keywords

Hardware/software Codesign, Heuristic Search, Multiple Neighborhood Functions
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  • Integrated Task Clustering, Mapping and Scheduling for Heterogeneous Computing Systems

Abstract Views: 336  |  PDF Views: 159

Authors

Yuet Ming Lam
Macau University of Science and Technology, China

Abstract


This paper presents a new approach for mapping and scheduling task graphs for heterogeneous hardware/software computing systems using heuristic search. Task mapping and scheduling are vital in hardware/software codesign and previous approaches that treat them separately lead to suboptimal solutions. In this paper, we propose two techniques to enhance the speedup of mapping/scheduling solutions: (1) an integrated technique combining task clustering, mapping, and scheduling, and (2) a multiple neighborhood function strategy. Our approach is demonstrated by case studies involving 40 randomly generated task graphs, as well as six applications. Experimental results show that our proposed approach outperforms a separate approach in terms of speedup by up to 18.3% for a system with a microprocessor, a floating-point digital signal processor, and an FPGA.

Keywords


Hardware/software Codesign, Heuristic Search, Multiple Neighborhood Functions