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International Journal of Innovative Research and Development, Vol 2, No 10 (2013), Pagination:
Abstract
Vedic mathematics is the ancient system of Indian mathematics. This paper suggests a method for VLSI implementation of the Vedic multiplication and division algorithms. It also attempts to perform a comparison based on speed, power, and area with conventional multiplication and division algorithms. Hence the vedic systems are better to the conventional systems, the vedic algorithms are used to implement the RSA encryption/decryption systems. RSA is the widely used public key encryption/decryption method. The Vedic RSA enabled the RSA hardware to work as fast as its software counterparts. Simulation is done in Verilog HDLwith Modelsim and Xilinx ISEsoftwares and implementation is on Xilinx Spartan 3E FPGA
Keywords
Vedic mathematics, RSA cryptography,Verilog HDL, modelsim, Xilinx Spartan 3E
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