Abstract
Contemporary digital systems use clocks for sequencing their operations and for synchronization among its functional block units. Clock frequencies and data transfer rates have been constantly increasing with every generation of processing technology. Phase locked-loops (PLLs) are widely used in order to generate well -timed on-chip clocks to be used in high performance digital systems. A PLL is a closed loop system in which that locks the phase of its output signal to an input reference signal. In the devices like computer, radio and telecommunications systems PLL’s are widely used, where it is necessary to stabilize a generated signal or to detect incoming signals. Advances in CMOS technology permits realization of high speed and low noise integrated frequency synthesizers and reduction in system costs.
The Phase-locked Loop (PLL) is referred to as an alias-locked loop (ALL) if it uses an aliasing divider in its feedback loop. With the use of an aliasing divider, the ALL architecture makes it possible to create high-speed frequency synthesis circuits without relying on a traditional divider clocked at fVCO in the feedback loop. In this design, I used five stage current starved VCO which provides both a high oscillating frequency and a wide tuning range. Here ALL is designed in 90-nm CMOS technology which locks the reference signal and the feedback signal i.e., VCO output in the range of 200MHz to 12.5GHz which consumes a power of 0.331mw with a supply voltage of 1.8v.
The schematics are designed and simulated using Cadence Virtuoso® Editor and Spectre® Simulator.
